1. Field of the Invention
The present invention relates to an architecture verifying apparatus, a method for verifying an architecture of a semiconductor integrated circuit, and a computer readable medium comprising a computer program code for verifying the architecture. In particular, the present invention relates to an architecture verifying apparatus, a method for verifying an architecture of a system LSI (Large Scale Integration), and a computer readable medium comprising a computer program code for verifying the architecture, which are used as tools for assisting to analyze the architecture.
2. Related Art
In ordinarily, performance of a system LSI largely depends upon an architecture of a system in use. Therefore, it is necessary to analyze the architecture of the system LSI in order to evaluate the performance of the system LSI.
For analyzing the architecture, however, it is necessary to regard a large amount of parameters such as selection of a processor included in the system, assignment of each processing executed on the system to the processor, processing time of each processing assigned to the processor, data transfer time on a bus, priority of the bus, the bus width, a bus arbitration method, the kind of a processor in use, and the operation frequency of the processor in use. Therefore, it is substantially impossible for a user to determine the architecture which fulfills specifications.
On the other hand, the architecture verifying apparatus is conventionally known as a tool used to assist to analyze the architecture when the user determines the architecture. The conventional architecture verifying apparatus makes a model operate on a simulator or a real machine to implement the architecture which is a candidate, acquire bus transactions issued to a bus, bus use wait information due to bus conflict, and throughput latency information of the bus, and display those kinds of information graphically to assist to make a determination whether the architecture fulfills specifications and to evaluate the architecture
However, it is difficult for the user to make a determination whether the architecture fulfills the specifications based on only those kinds of information. As a technique for solving such a problem, therefore, a technique in which application information and bus transactions are linked is known (see JP-A 2007-207120 (KOKAI)). According to the technique disclosed in JP-A 2007-207120 (KOKAI), the user can easily make a determination whether the architecture fulfills the specifications.
According to the technique disclosed in JP-A 2007-207120 (KOKAI), however, information concerning a change to be made on the architecture which does not fulfill the specifications in order to make the architecture fulfill the specifications is not given to the user. Therefore, it is necessary for the user to determine the architecture which fulfills the specifications through trial and error. As a result, the user's burden in the analysis of the architecture increases and the work time period required for the analysis becomes long.
On the other hand, in system LSI in recent years, importance of reduction of the power consumption has increased.
However, in the conventional architecture analysis, it is noted whether the architecture fulfills a time limit. Therefore, the architecture which fulfills the time limit is not necessarily the architecture which has the excellent power consumption. Furthermore, for designing an architecture which fulfills the time limit and which is low in power consumption, the user must go through trial and error. As a result, the user's burden for designing such an architecture increases and the work time becomes long.